Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produce a corresponding increase in overall chip failure rates at a time when chip failure rates must decrease to remain competitive. Chip manufacturers are therefore challenged to improve the quality of their products by identifying and eliminating defects which produce defective chips known as fails. Whereas significant improvements are being made to eliminate systematic defects by reducing process variability. Process improvements alone are not sufficient to eliminate all the random defects which affect both yield and reliability. Historically, screening techniques have been employed to improve product failure rates to acceptable levels by culling out many of these random defects.
During a typical plating process, a resist stencil is created on an underlying seed layer, generally a metal. The part is then normally immersed in a plating solution. This immersion process creates plated features wherever the resist is absent. Typically, the electroplated metal is copper. After plating, the resist is stripped and the underlying seed layer is given a flash etch, i.e., a short, timed etch. One of the problems with this prior art flash etching process of the seed layer is that it is not easy to control. For example, one could get under-etching of the seed layer which can cause shorts, while over-etching not only removes the metal in the seed layer, but will also etch the plated features, thus creating loss of copper from conductor lines and in some cases, opens or near-opens.
U.S. Pat. No. 5,382,447 (Kaja, et al.), the disclosure of which is incorporated herein by reference and presently assigned to the assignee of the instant patent application, discloses an electroless capping after the etching of the seed layer. A conductive metal, e.g. copper, is coated with a capping layer of a metal, e.g. cobalt, which capping layer is further characterized as having a thin layer of capping metal oxide adhered to the surface thereof.
Another problem that has also been observed on product parts is the interaction of copper with polyimide, which is applied subsequently. It has been noticed that the copper can react with the polyamic acid and this has the potential to degrade the electrical performance of the package, as the copper migrates into the polyimide layer during cure. See for example, G. Messner, et al., Thin Film Multichip Modules, p. 147 (1992).
U.S. Pat. No. 4,810,332 (Pan), discloses a method of making an electrical multilayer copper interconnect in which the electrical lines are protected by an electroplated overcoat. Preferably, before electroplating the overcoat, the copper is etched to expose the sides adjacent to the photoresist layer. This allows overcoating of all of the copper.
U.S. Pat. No. 5,071,518 (Pan), discloses a method of making an electrical multilayer interconnect in which the electrical lines are protected by an overcoat for corrosion resistance. This protective overcoat is deposited after the seed layer is removed by either electroless nickel or immersion coated tin.
Furthermore, for structures which employ subtractive etching of Cr/Cu/Cr to create wiring levels, the Cr capping layer does not cover the sidewalls, leaving the copper sidewall exposed during the copper etching step, and during subsequent processing. This exposure of the side wall in some cases leads to copper-polyimide interaction which can degrade the electrical performance of the structure.